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Substrate Power Integrity
At BroadPak no design has ever been signed off
without comprehensive power integrity analysis. In fact, during
the co-design process IR drop modeling and analysis is a routine
task and is well integrated into the substrate design flow.
BroadPak's flow not only predicts an accurate voltage profile
but also shows where the power integrity problems may exist so
the silicon design team can rectify them before tapeout.
Power delivery design and structure has first order effect on:
-- Simultaneously Switching Noise Output (SSO/SSN)
-- Core voltage stability
-- Silicon architecture, bump (pin out) topology
-- Substrate design
IR drop is a well known cause of chip failure at lower process
nodes. As the process node shrinks to 40nm and beyond, power
rail integrity issues are observed at the silicon level and in
the field for two chief reasons:
1- Deep-submicron designs require low power supply voltages,
this reduces the chip's threshold to noise (noise margin)
2- Deep-submicron designs results in many more transistors per
die. More transistors consume more power this will strain the
chip's power delivery network resulting in Dynamic Voltage Drop.
The importance of power integrity analysis at smaller process
nodes can't be emphasized more; conductor resistance, inductance
effects and capacitive parasitics results in IR drop.
Subsequently, IR drop causes delay and slew rate changes that
leads to set-up and hold-time violations. Set-up violation in
turn results in slow chip performance and hold-time violation
results in more severe chip failure.
Low threshold for noise margin makes the chip vulnerable to
glitches and failure. Decoupling caps used to ease the IR drop
if not used wisely are also a cause of increased power leakage.
It is important to realize that voltage drop not only varies
across the chip but also in time across the clock cycle as a
function of mode. Thus the factors that stress the power
delivery network must be included in the analysis.
At high speed, determining the frequency at which the cavity
formed between the power and ground plane resonate is the key to
a successful power delivery management. These resonances
are the major cause of SSO noise and cross-talk. |
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IR drop on a supply plane |
