The importance of power integrity analysis at smaller
process nodes can't be emphasized more; conductor
resistance, inductance effects and capacitive parasitics
results in IR drop. Subsequently, IR drop causes delay
and slew rate changes that leads to set-up and hold-time
violations. Set-up violation in turn results in slow
chip performance and hold-time violation results in more
severe chip failure.
Low threshold for noise margin makes the chip vulnerable
to glitches and failure. Decoupling caps used to ease
the IR drop if not used wisely are also a cause of
increased power leakage.
It is important to realize that voltage drop not only
varies across the chip but also in time across the clock
cycle as a function of mode. Thus the factors that stress the power delivery network must be included in
At high speed, determining the frequency at which the
cavity formed between the power and ground plane
resonate is the key to a successful power delivery
management. These resonances are the major cause of SSO
noise and cross-talk.