Thermal management is vital for the performance,
reliability and lifetime of high-speed packages and
systems. BroadPak offers comprehensive thermal
management solution to aid in package selection as well
as post design and system level simulation and analysis.
Designing package substrate with low thermal tolerance
can be costly since it can lead to overheating and
failure of the chip. BroadPak guarantees an optimal
thermal design of cost verses performance. Facts about
seriousness of thermal management:
-- With the increase in temperature leakage increase
-- At 65nm leakage counts for 70% of total power loss
-- Increase in temperature has adverse effect on timing
-- Electromigration increases exponentially with
-- Resistant is linearly dependent on temperature,
effecting IR drop
-- Clock gating increases on-chip thermal variation
It is important to account for power leakage in addition
to on-chip temperature, electromigration, reliability
and IR drop during thermal analysis. One of the key
challenges at 40nm is managing thermal effects with
regards to timing, signal and power integrity.
In vast majority of the thermal analysis done today,
temperature is assumed to be constant across the surface
of the silicon chip. But, in reality, today's large and
dense dice can exhibit significant thermal gradient
across the surface of the die and the device layers.
Depending on the switching activity of the device,
temperature as much as 40 degree Celsius can vary cross
the surface of the chip. Similarly, the same gradient
can occur across the device layers.
This variation in temperature across the die as well as
mismatch in coefficient of thermal expansion (CTE)
between the die and substrate can cause warpage, die
crack and/or solder joint crack/short.
During the package development phase BroadPak can
determine possible failure scenarios such as cracks,
interfacial delimitation and popcorning, etc. through
conjugate thermo-fluid and structural-stress analysis.