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BroadPak Corp.
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Signal Integrity

 


Substrate signal integrity

At BroadPak signal integrity is an integral part of the substrate design process. With years of experience and leading edge designs, BroadPak is renowned for excellence in signal integrity. As fabrication process node shrinks and signal slew rate gets faster, signal integrity issues are eminent.

At higher speed substrate must be able to support very fast varying broadband signals with superb signal fidelity. Poor signal integrity means added costs, delayed product releases and lost revenue.
 


Serial Link (SER/DES) Interfaces

With an architectural shift from parallel link to serial link (XAUI, RXAUI, 10G, PCIE, SATA, Fiber Channel, ...) new challenges have emerged due to increased data rate and throughput requirement. High frequency analog effects such as reflection, ground bounce, cross talk and propagation delays through the substrate adversely effects the signal quality and timing performance.

Effect of via discontinuity is significantly amplified at higher frequencies. At 10 gigabit per second and beyond, via optimization is mandated to minimize reflection. At BroadPak all the elements of the interconnect are optimized to maximize performance.

 

 

High Speed DDR-II / DDR-III Interfaces

BroadPak has wealth of experience designing high performance memory substrates and modules to operate at maximum clock frequency. As the demand for high bandwidth memory product increases signal integrity issues in designing such systems also increases. Although the speed of DDR-II/DDR/III is not as high as Serial Link interfaces, however, signal integrity issues are significantly challenging.

This is due to the parallel verses serial nature of these interfaces. For example at DDRII-667 and 800 MHz tens of picoseconds is significant in closing the timing budget. Reflection, ringing and x-talk noise is real serious with the increase in signal speed of parallel busses.


With the industry shift toward DDR-III and higher data rate, the period during which data can be reliably latched (data valid window) for read by the controller and write by the memory device is shrinking. The data valid window shrinkage is due to uncertainties associated with the parameter variation such as clock, jitter, device process and system power.

That is why at BroadPak signal integrity, power integrity and timing analysis (setup / hold time margin) are performed simultaneously.
 
   
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