High Speed DDR-II / DDR-III Interfaces
BroadPak has wealth of experience designing high
performance memory substrates and modules to operate at
maximum clock frequency. As the demand for high
bandwidth memory product increases signal integrity
issues in designing such systems also increases.
Although the speed of DDR-II/DDR/III is not as high as
Serial Link interfaces, however, signal integrity issues
are significantly challenging.
This is due to the parallel verses serial nature of
these interfaces. For example at DDRII-667 and 800 MHz
tens of picoseconds is significant in closing the timing
budget. Reflection, ringing and x-talk noise is real
serious with the increase in signal speed of parallel
With the industry shift toward DDR-III and higher data
rate, the period during which data can be reliably
latched (data valid window) for read by the controller
and write by the memory device is shrinking. The data
valid window shrinkage is due to uncertainties
associated with the parameter variation such as clock,
jitter, device process and system power.
That is why at BroadPak signal integrity, power
integrity and timing analysis (setup / hold time margin)
are performed simultaneously.